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Lisa Su: Venice and Verano CPUs designed with 2-nanometer process and Zen 6 architecture; Verano is first EPYC CPU purpose-built for AI infrastructure, extending competitive advantage over x86 and ARM alternatives
Lisa Su· AMD· AI· 2026-05-06· about AMD, TSMC (implied) (AMD)
“Our sixth-gen EPYC Venice processor built on our Zen 6 architecture and 2-nanometer process technology is designed to extend our leadership across cloud, enterprise and AI workloads... delivering substantially higher performance per socket and per watt versus competitive x86 offerings and more than 2x throughput per socket versus leading ARM-based AI solutions.”
Why it matters
Venice on 2nm represents significant R&D investment and TSMC capacity allocation. Purpose-built Verano SKU indicates AMD is segmenting the AI infrastructure market and building specialized products, not just repurposing existing designs.
Investment implication
TSMC will see sustained 2nm node demand for Venice ramps starting H2 2026. EDA and design services supporting 2nm AI-optimized CPU design will benefit. Memory and power delivery suppliers will need to optimize for higher transistor density and performance.