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Scale-up networking (Ethernet and UALink switching fabric for XPU interconnect) is becoming critical XPU attach category; Marvell targeting product introductions in next 2 years, leveraging Inphi low-latency switching IP and proprietary SerDes
Matt Murphy· Marvell Technology· AI· 2026-07-24· about Marvell Technology (acquired Inphi for scale-up switching IP) (MRVL)
“As next-generation AI data centers evolve, scale-up networks are becoming essential to tightly interconnect tens, hundreds, and eventually thousands of XPUs within and across racks... Marvell's multi-generational custom engagements with the hyperscalers gives us unique visibility into upcoming XPU architectures, enabling us to design scale-up switches supporting both open standard Ethernet and UALink fabrics purpose-built for AI... product introductions in the UA link and Ethernet space for scale up specifically will be in the next 2 years.”
Why it matters
Scale-up switching is emerging as a mandatory component in large-scale AI training clusters to replace or augment copper-based interconnects. Marvell's Inphi acquisition positioned it to address this via low-latency Ethernet and UALink switch fabrics, creating a new high-margin XPU attach category beyond custom chips themselves.
Investment implication
Companies providing high-speed switch silicon (Marvell via Inphi IP, potentially others), low-latency SerDes IP vendors, and optical interconnect components (DSPs for AECs and AOCs) will benefit from mandatory scale-up fabric adoption. This represents a pick-and-shovel opportunity adjacent to XPU design wins and will drive incremental capex on networking silicon and optical modules for hyperscalers.