bottleneckScore 100/100Research
Marvell securing 3nm wafer and advanced packaging capacity for XPU production in calendar 2026; custom silicon revenue accelerating with 18+ design wins across hyperscalers
Matt Murphy· Marvell Technology· AI· 2026-07-24· about Marvell Technology (MRVL)
“I think last earnings call, Matt, you talked about securing 3 nanometer wafer capacity, packaging capacity production in calendar 2026. Is this program still tracking? What's the confidence level on this program still driving growth next year?... [Matt responds affirming the program is tracking and then pivots to focus on collective design wins rather than individual socket commentary]”
Why it matters
Marvell is explicitly securing advanced 3nm wafer and packaging capacity ahead of major XPU production ramps, signaling tight constraints in foundry and advanced packaging capacity during a critical period of AI infrastructure buildout. This suggests TSMC and advanced packaging providers (like TSMC's CoWoS) face competing demand.
Investment implication
TSMC and advanced packaging capacity providers (particularly those serving 3nm and advanced CoWoS/chiplet packaging) are becoming critical bottlenecks for AI chip production. Investors should monitor TSMC's guidance on 3nm capacity allocation and advanced packaging utilization rates. Equipment vendors serving advanced packaging (ASM, ASML, Tokyo Electron) may see sustained demand acceleration.